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ST
Sitronix
1. INTRODUCTION
fewest components.
ST7573
132 x 33 Dot Matrix LCD Controller/Driver
ST7573 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. ST7573 contains 132 segment and 33 common driver circuits. This chip is connected directly to a microprocessor, accepts 3-line, 4-line serial peripheral interface (SPI) or 8-bit parallel interface, display data can stores in an on-chip Display Data RAM (DDRAM) of 132 x 33 bits. It performs Display Data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible to make a display system with the
2. FEATURES
Single-chip LCD controller & driver Driver Output Circuits 132 segments / 32 commons + 1 ICON common 132 segments / 16 commons + 1 ICON common 132 segments / 8 commons + 1 ICON common On-chip Display Data RAM (DDRAM) Capacity: 132X33=4356 bits Microprocessor Interface 8-bit parallel bi-directional interface with 6800-series or 8080-series 4-line SPI (serial peripheral interface) available (only write operation) 3-line SPI (serial peripheral interface) available On-chip Low Power Analog Circuit Embedded Boosters with voltage regulation function that generates high-accuracy voltage. Voltage regulation temperature gradient -0.07%/ C Programmable Booster stages: X3,X4. On-chip electronic contrast control function Built-in Voltage Follower generates LCD bias voltages (1/4 to 1/7). Built-in oscillator Built-in oscillator requires no external components (external clock input is also supported) External RESB (reset) pin Supply voltage range VDD - VSS (Digital): 2.4 to 3.3V (typical); VDD2 - VSS (Analog): 2.4 to 3.3V (typical). Display supply voltage range Programmable voltage (LCD Vop): 8.31V (max) Temperature range: -30 to +85 degree
ST7573
6800 , 8080 , 4-Line , 3-Line interface
Ver 1.0b
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1 267
5~6
1~5
Ver 1.0b
Chip Size:
VDD2 VDD2 VDD VDD VDD
PAD
6~11
11~12
49~50
40~49
39~40
12~39
265 264
PAD Pitch:
Bump Height:
Rough layout
ST7573
6 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY
Reserve Reserve Reserve COMS2 COM15 COM14
Chip Thickness: 480m
12
60.0 84.5 60.0
84.5
Pitch
15m
70.0
60.0
89.0
60.0
248
73~96
72~73
50~72
97~115
115~116
116~247
248~267
247~248
24
COM1 COM0 SEG131 SEG130 SEG129 SEG128 SEG127
PAD
6074m(X) x 720m(Y)
31
57.0
34.0
34.0
60.0
70.0
60.0
Pitch
34.0
57.0
37
Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse PS0 PS1 PS2 MLB T11 PM T10 VDD VDD VDD VDD2 VDD2 VDD2 VM VM VM
40
3. ST7573 Pad Arrangement (COG)
For easy LCM design, the Power-1, Power-2 & Power-3 are identical (any one of them can be used).
Power-3 has VGI, VGS, V0O, V0I, V0S, XV0O, XV0I and XV0S which are not in Power-1 or Power-2.
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47 55 50 118 57 64 68 V0O V0O V0S V0I V0I V0I V0I XV0I XV0I XV0I XV0I XV0S XV0O XV0O T1 T2 T3 T4 T0 T5 T6 T7 T8 74 116 114 113 82 SEG4 SEG3 SEG2 SEG1 SEG0 Reserve Reserve COMS1 COM16 COM17 COM18 87 89 96 T9 D7 D6 D5 D4 D3 D2 D1 D0 ERD RWR A0 CSB OSC RESB VRS VDD VDD VDD VDD VDD2 VDD2 VDD2 VDD2 COM29 COM30 COM31 97
VGI VGI VGI VGI VGS VGO VGO VSS VSS VSS
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ST7573
4. Pad Center Coordinates
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 PAD Name VDD2 VDD2 VDD VDD VDD DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve PS0 PS1 PS2 MLB T11 PM T10 VDD VDD VDD VDD2 VDD2 VDD2 VM VM VM VGI VGI VGI VGI VGS VGO X -2899.00 -2839.00 -2779.00 -2719.00 -2659.00 -2574.50 -2514.50 -2454.50 -2394.50 -2334.50 -2274.50 -2190.00 -2130.00 -2070.00 -2010.00 -1950.00 -1890.00 -1830.00 -1770.00 -1710.00 -1650.00 -1590.00 -1530.00 -1470.00 -1410.00 -1350.00 -1290.00 -1230.00 -1170.00 -1110.00 -1050.00 -990.00 -930.00 -870.00 -810.00 -750.00 -690.00 -630.00 -570.00 -481.00 -421.00 -361.00 -301.00 -241.00 -181.00 Y -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 PAD No. 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 PAD Name VGO VSS VSS VSS V0O V0O V0S V0I V0I V0I V0I XV0I XV0I XV0I XV0I XV0S XV0O XV0O T1 T2 T3 T4 T0 T5 T6 T7 T8 T9 D7 D6 D5 D4 D3 D2 D1 D0 ERD RWR A0 CSB OSC RESB VRS VDD VDD X -121.00 -61.00 -1.00 59.00 129.00 189.00 249.00 309.00 369.00 429.00 489.00 549.00 609.00 669.00 729.00 789.00 849.00 909.00 969.00 1029.00 1089.00 1149.00 1209.00 1269.00 1329.00 1389.00 1449.00 1519.00 1579.00 1639.00 1699.00 1759.00 1819.00 1879.00 1939.00 1999.00 2059.00 2119.00 2179.00 2239.00 2299.00 2359.00 2419.00 2479.00 2539.00 Y -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 -286.50
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PAD No. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 PAD Name VDD VDD VDD2 VDD2 VDD2 VDD2 COM[31] COM[30] COM[29] COM[28] COM[27] COM[26] COM[25] COM[24] COM[23] COM[22] COM[21] COM[20] COM[19] COM[18] COM[17] COM[16] COMS1 Reserve Reserve SEG[0] SEG[1] SEG[2] SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] X 2599.00 2659.00 2719.00 2779.00 2839.00 2899.00 2913.00 2879.00 2845.00 2811.00 2777.00 2743.00 2709.00 2675.00 2641.00 2607.00 2573.00 2539.00 2505.00 2471.00 2437.00 2403.00 2369.00 2335.00 2301.00 2244.00 2210.00 2176.00 2142.00 2108.00 2074.00 2040.00 2006.00 1972.00 1938.00 1904.00 1870.00 1836.00 1802.00 1768.00 1734.00 1700.00 1666.00 1632.00 1598.00 Y -286.50 -286.50 -286.50 -286.50 -286.50 -286.50 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 PAD No. 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 PAD Name SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] X 1564.00 1530.00 1496.00 1462.00 1428.00 1394.00 1360.00 1326.00 1292.00 1258.00 1224.00 1190.00 1156.00 1122.00 1088.00 1054.00 1020.00 986.00 952.00 918.00 884.00 850.00 816.00 782.00 748.00 714.00 680.00 646.00 612.00 578.00 544.00 510.00 476.00 442.00 408.00 374.00 340.00 306.00 272.00 238.00 204.00 170.00 136.00 102.00 68.00 Y 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00
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PAD No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 PAD Name SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] SEG[102] SEG[103] SEG[104] SEG[105] SEG[106] SEG[107] SEG[108] SEG[109] X 34.00 0.00 -34.00 -68.00 -102.00 -136.00 -170.00 -204.00 -238.00 -272.00 -306.00 -340.00 -374.00 -408.00 -442.00 -476.00 -510.00 -544.00 -578.00 -612.00 -646.00 -680.00 -714.00 -748.00 -782.00 -816.00 -850.00 -884.00 -918.00 -952.00 -986.00 -1020.00 -1054.00 -1088.00 -1122.00 -1156.00 -1190.00 -1224.00 -1258.00 -1292.00 -1326.00 -1360.00 -1394.00 -1428.00 -1462.00 Y 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 * Unit: m PAD No. 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 PAD Name SEG[110] SEG[111] SEG[112] SEG[113] SEG[114] SEG[115] SEG[116] SEG[117] SEG[118] SEG[119] SEG[120] SEG[121] SEG[122] SEG[123] SEG[124] SEG[125] SEG[126] SEG[127] SEG[128] SEG[129] SEG[130] SEG[131] COM[0] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COMS2 Reserve Reserve Reserve X -1496.00 -1530.00 -1564.00 -1598.00 -1632.00 -1666.00 -1700.00 -1734.00 -1768.00 -1802.00 -1836.00 -1870.00 -1904.00 -1938.00 -1972.00 -2006.00 -2040.00 -2074.00 -2108.00 -2142.00 -2176.00 -2210.00 -2267.00 -2301.00 -2335.00 -2369.00 -2403.00 -2437.00 -2471.00 -2505.00 -2539.00 -2573.00 -2607.00 -2641.00 -2675.00 -2709.00 -2743.00 -2777.00 -2811.00 -2845.00 -2879.00 -2913.00 Y 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00 255.00
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5. BLOCK DIAGRAM
COM0 SEG131
COMS COM31
SEG0
VM VGI VGO VGS XV0I XV0O XV0S V0I V0O V0S
Voltage Follower VG Generator XV0 Generator V0 Generator Power System
COMS
SEGMENT Drivers
COMMON Drivers
Display Data Latchs
COMMON Output Controller DTY Timing Generator Oscillator OSC
PM
Display Data RAM (DDRAM) 132X33
VDD2 VDD VSS Data Register Address Counter Control Registers
Command Decoder Reset Circuit
MPU INTERFACE ( Parallel / Serial )
RESB
MLB
Figure 1
D7 D6 D5 D4 D3 D2 D1 D0 /RD (E) /WR (R/W) A0 CSB
PS2 PS1 PS0
Block Diagram
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6. PIN DESCRIPTION
Pin Name I/O Description Pin Count LCD DRIVER OUTPUTS LCD segment driver outputs. This display data and the M signal control the output voltage of segment driver. Display data SEG0...SEG131 O H H L L Frame + + Segment driver output voltage Normal display VG VSS VSS VG VSS Reverse display VSS VG VG VSS VSS 132
Power save mode LCD column driver outputs.
This internal scanning data and M signal control the output voltage of common driver. Display data COM0...COM31 O H H L L Frame + + Common driver output voltage Normal display XV0 V0 VM VM VSS 2 Reverse display 32
Power save mode COMS1...COMS2 O When not used, this pin should be floating. Microprocessor interface select input pin. PS2 PS0...PS2 I "L" "H" "L" "H" CSB I PS1 "L" "L" "H" "H" PS0 "L" "L" "L" "L"
Common output for the icon. The output signals of two pins are the same.
MICROPROCESSOR INTERFACE State 4 Pin-SPI MPU interface 3 Pin-SPI MPU interface 8080-series parallel MPU interface 6800-series parallel MPU interface 1 3
Chip select input pins. Data/instruction I/O is enabled only when CSB is "L". When chip select is non-active, D0 to D7 is high impedance. RESB I Reset input pin. When RESB is "L", initialization is executed. It determines whether the data bits are data or a command. A0 I A0="H": Indicates that D0 to D7 are display data. A0="L": Indicates that D0 to D7 are control data. When in 3-line SPI interface, left it connected to VDD. 1 1
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Read/Write execution control pin (PS[0:1]=[L:H]). PS2 H RWR I L 8080-series /WR MPU type 6800-series RWR R/W Description Read/Write control input pin R/W="H": read; R/W="L": write. Write enable clock input pin The data on D0 to D7 are latched at the rising edge of the /WR signal. When in the serial interface, left it connected to VDD. Read/Write execution control pin (PS[0:1]=[L:H]). PS2 MPU Type /RD(E) Description Read/Write control input pin R/W="H": When E is "H", D0 to D7 H ERD I 6800-series E are in an output status; R/W="L": The data on D0 to D7 are latched at the falling edge of the E signal. Read enable clock input pin. L 8080-series /RD When /RD is "L", D0 to D7 are in an output status. When in the serial interface, left it connected to VDD. When using 8-bit parallel interface: 6800, 8080 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When chip select is not active, D0 to D7 is high impedance. When using serial interface: 4-LINE D0: serial input clock (SCLK); D7...D0 I/O D1, D2, D3: serial input data (SDA), must be connected together; D4~D7 must be connected to VDD (not used). When chip select is not active, D0 to D7 is high impedance. When using serial interface: 3-LINE D0: serial input clock (SCLK). D1, D2, D3: serial input data (SDA), must be connected together; D4~D7 must be connected to VDD (not used). When chip select is not active, D0 to D7 is high impedance. 8 1 1
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LCD DRIVER CLOCK SUPPLY When the on-chip oscillator is used, this input must be connected to VDD. An external clock signal, if used, is connected to this pin. The OSC I oscillator and external clock are both inhibited by connecting the OSC pin to VSS and the display is not clocked and may be left in a DC state. To avoid this, the chip should always be put into Power Down Mode before stopping the clock. POWER SUPPLY PIN VSS Power Ground. Digital Supply voltage. VDD Power The 2 supply rails, VDD and VDD2 , could be connected together (for single power). If a Digital Option pin is high, must be this level. Analog Supply voltage. VDD2 VRS Power Power The 2 supply rails, VDD and VDD2 , could be connected together (for single power). Reference voltage. Must be left open. Positive LCD driving voltage for commons. V0I is the V0 power source for the LCD driver. If using external V0, apply V0I, V0O, V0S Power the external power source on these pads. V0O is the internal V0 regulator output pad. V0S is the feedback for the internal V0 voltage compensation circuit. They should be separate in ITO and be connected together by FPC. Negative LCD driving voltage for commons. XV0I is the XV0 power source for the LCD driver. If using external XV0, XV0I, XV0O,XV0S Power apply the external power source on these pads. XV0O is the internal XV0 regulator output pad. XV0S is the feedback for the internal XV0 voltage compensation circuit. They should be separate in ITO and be connected together by FPC. 7 7 1 9 10 3 1
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LCD driving voltage for segments. VGI is the VG power source for the LCD driver. If using external VG, apply VGI, VGO, VGS Power external power source on these pads. VGO is the internal VG regulator output pad. VGS is the feedback for the internal VG voltage compensation circuit. They should be separate in ITO and be connected together by FPC. VM Power LCD driving voltage for commons. Data format (MSB on top or LSB on top). MLB I MLB="H", MSB on top (D7 on top); MLB="L", LSB on top (D0 on top). Set power mode. This pin will change the V0 (Vop) formula parameter. PM I V0=( a + VOP[6:0] x b ) PM="L", a=3.0V, b=0.03V; PM="H", a=4.5V, b=0.03V. TEST PIN T0~T8: left them open. T0...T11 Test T9 must connect to VSS. T10 and T11 must connect to VDD. The unused pins should be left floating. The Microprocessor Interface pins should not be left floating under any operation mode. Recommend I/O pins ITO Resistance Limitation Pin Name VRS, T[8:0] VSS VDD VDD2 V0 (V0I + V0O + V0S), XV0 (XV0I + XV0O + XV0S), VG (VGI + VGO + VGS), VM CSB, A0, /RD, /WR, D[7:0] PS[2:0], OSC , MLB, T[11:9] RESB Notes: 1. If using internal clock, OSC is connect to VDD and the limitation of ITO resistance will be "No Limitation". If using external clock, the ITO resistance of OSC should be kept lower than 500 to keep the clock signal quality.
*1
7
3
CONFIGURATION PIN 1
1
12
ITO Resistance Floating <100 <100 <100 <500 <1K <5K <10K
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7. FUNCTIONS DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
The CSB pin is used for chip selection. ST7573 can interface with an MPU when CSB is "L". When CSB is "H", the control pins (A0, /RD and /WR) are disabled and D0 to D7 are set to be high impedance. If using serial interface, the internal shift register and the counter are reset when CSB="H".
Parallel / Serial Interface
ST7573 has five types of interface to communicate with an MPU, which are three serial and two parallel interfaces. The parallel or serial interface is determined by PS[2:0] pin as shown below. Table 1 PS2 "L" "H" "L" "H" PS1 "L" "L" "H" "H" PS0 "L" "L" "L" "L" Parallel/Serial Interface Selection CSB CSB CSB CSB CSB A0 A0 "H" A0 A0 State 4 Pin-SPI MPU interface 3 Pin-SPI MPU interface 8080-series parallel MPU interface 6800-series parallel MPU interface
Parallel Interface
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS[2:0] as shown in Table 2. The type of data transfer is determined by A0, ERD and RWR as shown in Table 3. Table 2 PS2 H L PS1 H H PS0 L L CSB CSB CSB Microprocessor Selection for Parallel Interface A0 A0 A0 Table 3 Common A0 H H L L 6800-series E (/RD) H H H H R/W (/WR) H L H L /RD (E) L H L H ERD E /RD RWR R/W /WR DB0 to DB7 DB0 to DB7 DB0 to DB7 MPU bus 6800-series 8080-series
Parallel Data Transfer 8080-series /WR (R/W) H L H L Display data read out Display data write Register status read Writes to internal register (instruction) Description
NOTE: When ERD pin is always pulled high in 6800-series interface, the CSB can be used as enable signal. In this case, interface data is latched at the rising edge of CSB and the access type is determined by A0, RWR as 6800-series mode.
Serial Interface
ST7573 supports 3 kinds of serial interface and the type is selected by PS2~PS0 as shown below. Serial Mode 4-line SPI interface 3-line SPI interface PS2 L H PS1 L L PS0 L L CSB CSB CSB A0 A0 Not Used Fix to "H"
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PS2="L", PS1="L", PS0="L": 4-line SPI interface
When ST7573 is set into 4-line SPI interface mode, setting CSB to be "L" will active this chip. If CSB is "H", the internal 8-bit shift register and a 3-bit counter are reset. When CSB is "L", the serial data (SDA) and the serial clock (SCLK) are set into input mode. The input signal on SDA will be latched into the shift register from D7 to D0 at the rising edge of the serial clock. The display data/instruction indication is controlled via the register select pin: A0. If A0="L", the input signal on SDA will be treated as instruction; if A0="H", the input signal on SDA will be treated as data. After 8-bit data are written into the Data Display RAM, the DDRAM column address pointer will be increased by one automatically.
Figure 2
4-line SPI Timing
PS2="H", PS1="L", PS0="L": 3-line SPI interface
Because 3-line SPI interface mode does not have a register selection pin "A0", this mode latches the A0 bit first and then latches 8-bit input (please refer to the following figure).
Figure 3
3-line SPI Timing
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Data Transfer
ST7573 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Figure 4. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in Figure 5. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.
Figure 4
MPU signal A0 /WR D0 to D7 Internal signals /WR BUS HOLDER COLUMN ADDRESS N N
Write Timing
D(N)
D(N+1) D(N+2)
D(N+3)
D(N) N
D(N+1) N+1
D(N+2) N+2
D(N+3) N+3
Figure 5
MPU signal A0 /W R /RD D0 to D7 Internal signals /W R /RD BUS HOLDER COLUMN ADDRESS N N
Read Timing
Dum m y
D(N)
D(N+1)
D(N) N D(N)
D(N+1) D(N+1)
D(N+2) D(N+2)
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ST7573
DISPLAY DATA RAM (DDRAM)
ST7573 contains a 132X33 bit static RAM that stores the display data. The Display Data RAM stores the dot data for the LCD display. It is 132-column by 33-row addressable array: 132X33 (4-page X 8-bit + 1-page X 1-bit). Each pixel can be selected when the page and column addresses are specified. The 33 rows are divided into 4 pages (with 8 lines, COM 0~31) and the 4th page (with 1 lines, COMS). Data is read from or written to each page directly through D7 to D0. The display data (D7~D0) corresponds to the LCD common-line direction (default: top to down). The microprocessor can write to and read (only Parallel interfaces) from DDRAM by the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker or data-conflict.
DDRAM ORGANIZATION
Data is written in bytes into the RAM matrix of ST7573 as shown in Figure 6~Figure 9. The Display Data RAM is a matrix of 132 by 33 bits. The address pointer keeps the X and Y address. The valid address ranges are: X=0~131, Y=0~4. The default data orientation of DDRAM is controlled by the hardware pin "MLB". When MLB="L", the data write into DDRAM is from D0~D7 (LSB on top). Please refer to Figure 6. When MLB="H", the data write into DDRAM is from D7~D0 (MSB on top). Please refer to Figure 7.
Figure 6
DDRAM Format, If MLB=0
Figure 7
DDRAM Format, If MLB=1
COLUMN ADDRESS CIRCUIT
Column Address Circuit has an 8-bit preset counter that points to each column of DDRAM as shown in Figure 6. The valid range is from 0 to 131. The DDRAM column address can be specified by the Set X address instruction.
PAGE ADDRESS CIRCUIT
This circuit is for providing a page address to Display Data RAM. It incorporates 3-bit Y address register and can be programmed by the "Set Y address of RAM" instruction. Page Address 4 is a special RAM area for icon (please refer to Figure 6 & Figure 7).
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START LINE ADDRESS CIRCUIT
This circuit assigns DDRAM a line address that is scanned first at the beginning of each frame. By setting Start Line Address repeatedly, the display pattern looks like scrolling vertically in the screen without changing the contents of DDRAM (refer to Figure 11). When setting the Start Line Address (with "Set Start Line" instruction), the data of the same specified line address in DDRAM are transferred to the Display Data Latch Circuit at the beginning of each frame. If icon is used, icon RAM will not be scrolled with DDRAM.
ADDRESSING
ST7573 will automatically increases the address when sequential access. This feature allows MPU to access the display data in DDRAM continuously without setting the address before each access. In horizontal addressing mode, the X address is automatically increased by 1 after each byte access (refer to Figure 8). After the last X address (X=131), X address wraps around to 0 and Y address increases to the next page. After the very last address (X=131, Y=4), the address pointers wrap around to the original address (X=0, Y=0). In vertical addressing mode, the Y address is automatically increased by 1 after each byte access (refer to Figure 9). After the last Y address (Y=4), Y address wraps around to 0 and X address increases to the next column. After the very last address (X=131, Y=4), the address pointers wrap around to the original address (X=0, Y=0).
Figure 8
Addressing Mode: Horizontal (V=0)
Figure 9
Addressing Mode: Vertical (V=1)
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LCD DRIVER DISPLAY DIRECTION
Register bits XD (horizontal direction) and MY (vertical mirror) control the horizontal and vertical display direction. XD controls the X-address write direction in DDRAM while MY controls the common output direction. Therefore, it is necessary to rewrite the display data to DDRAM after changing XD-bit setting. Refer to the following figure.
COM
Y Address Y2 Y1 Y0
Data Format
1/33 Duty MY=0 MY=1
1/9 Duty MY=0 MY=1
1/17 Duty MY=0 MY=1 PAD
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
MLB=0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0
MLB=1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7
BBB B B BBB B BBB BBB B B B B B BBB BBBBB B B B B B B BBBB B B B B BBBB B B B B B B B B B
Page 0
Page 1
Page 2
Page 3
Page 4
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COMS
COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC COMS
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC COMS
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS
248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 113, 264
XD=1 XD=0
Figure 10 LCD Driver Display Direction
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DDRAM MAP vs. START LINE
Figure 11 Display Data RAM Map (33 COM)
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ST7573
LCD DRIVER CIRCUIT
ST7573 built-in LCD driver circuit has 132-channel segment drivers and 33-channel common drivers. The LCD panel driving voltage depends on the combination of display data and M signal (frame indicator).
Figure 12 External Power Parts
IC Internal V0 Generator VG Grnerator VDD2 VSS XV0 Generator VSS XV0 V0
C2
IC External
R1
VG
C1
C1: 0.1uF~1.0uF (Non-Polar/6V) C2: 0.1uF~1.0uF (Non-Polar/16V) R1: Reserve (Default NC.)
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ST7573
PARTIAL DISPLAY (SOFTWARE)
The Partial Display function is controlled by software instruction. This feature is available under 1/9 duty mode and 1/17 duty mode. If duty mode is 1/33, the function of Partial Display is ineffective. The start common of Partial Display function is selected by "Display Part" command. Through combining the commands of "Display Duty" and "Display Part", there are 6 options for Partial Display operation (Figure 13~ Figure 14 referred to explain 3 kinds of Partial Display operation).
Figure 15 Partial Display OFF
Figure 16 Partial Display: 1/17 Duty, (DP[1:0]=0,0)
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Figure 17 Partial Display: 1/17 Duty, (DP[1:0]=0,1)
Figure 18 Partial Display: 1/9 Duty, (DP[1:0]=1,0)
COM0 COM1 COM2 COM3 COM4 COM5 COM6
COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31
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8. RESET CIRCUIT
Setting RESB to "L" can initialize internal function. While RESB is "L", no instruction except read status can be accepted. The initialization by RESB is essential before using. When RESB becomes "L", the following procedures will start. Fix COM/SEG outputs at VSS. Page address: Y[2:0]=0 Column address: X[7:0]=0 COM Scan Direction MY=0 SEG Select Direction XD=1 Data Format: MLB=MLB pin setting Power down mode: PD=1 Initial V0 setting: VOP[6:0]=0 Display control: Display Blank: D=E=0 Normal instruction set: H=0 Frame Rate = 73Hz. FR[2:0]=011b Display Duty = 33 Duty Display Part = COM0 Booster setting: BE=0, PC[1:0]=01b (Booster Efficiency Level 2, Booster X3) Bias system: BS[1:0]=[0,0] (1/7 Bias) After power-on, RAM data are undefined and the Display status is "Blank". It's better to initialize whole DDRAM (fill all 00h or write the display pattern) before turning the Display ON.
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9. INSTRUCTION TABLE
INSTRUCTION A0 R/W (/WR)
0 0
COMMAND BYTE D7
0 0
D6
0 0
D5
0 0
D4
0 0
D3
0 0
D2
0 0
D1
0 0
D0
0 1
DESCRIPTION
H=0 or 1 (Independent of H)
NOP Reset
0 0
No Operation. Software Reset Scan direction (COM/SEG); Power mode (ON/OFF); Addressing mode; Instruction table selection. Read status (setting). Read DDRAM data. Write data into DDRAM.
Function Set
0
0
0
0
1
MY
XD
PD
V
H
Read Status Read Data Write Data
0 1 1
1 1 0
PD D7 D7
0 D6 D6
D D5 D5
E D4 D4
XD D3 D3
MY D2 D2
V D1 D1
MLB D0 D0
INSTRUCTION H=0
Reserved End read-modify-write Enable read-modify-write Display Control Frame Rate Set Y address of DDRAM Set X address of DDRAM (Low) Set X address of DDRAM (High)
A0
R/W (/WR)
0 0
COMMAND BYTE D7
0 0
D6
0 0
D5
0 0
D4
0 0
D3
0 0
D2
0 1
D1
1 1
D0
X 0
DESCRIPTION
0 0
Do NOT use. End Read-Modify-Write Enable Read-Modify-Write Set display configuration. Frame Rate control Set DDRAM Y address (0Y4) Set DDRAM X address Set the high-nibble first and then low-nibble. (0X131) Do NOT use. Set display duty Control booster stages and booster efficiency. Set display part for partial mode Set BIAS system. Set V0 voltage to register. Specify the first scan line in the DDRAM.
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
0 0 1 0
0 1 0 0
1 D FR2 Y2
1 0 FR1 Y1
1 E FR0 Y0
0
0
1
0
0
0
X3
X2
X1
X0
0
0
1
0
0
1
X7
X6
X5
X4
H=1
Reserved Display Duty Booster Control Display Part BIAS System Set V0 Set Start Line (Vertical-Scroll) 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 BE 1 PS PC1 X WS PC0
0 0 1 0
0 0 VOP6 1
0 0 VOP5 0
1 1 VOP4 S4
0 0 VOP3 S3
0 1 VOP2 S2
DP1 BS1 VOP1 S1
DP0 BS0 VOP0 S0
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10. INSTRUCTION DESCRIPTION
Function Set
A0
0
R/W(/WR)
0
D7
0
D6
0
D5
1
D4
MY
D3
XD
D2
PD
D1
V
D0
H
Flag
Set COM scan direction: MY
Description
MY=0: Normal direction (COM0->COM31, duty is determined by the "Display Duty" setting); MY=1: Reverse direction (COM31->COM0, duty is determined by the "Display Duty" setting). Set DDRAM write direction.
XD
XD=1: Write from X=0 to X=131 (Normal direction); XD=0: Write from X=131 to X=0 (Reverse direction). Set the power mode: PD=0: Chip is active; PD=1: Chip is in power save mode. In power save mode, all LCD outputs at VSS, built-in power circuits (Booster, Regulator and Follower) are turned OFF, Oscillator OFF (external clock is possible), RAM contents is not cleared; RAM data can be written. Select Vertical or Horizontal addressing mode.
PD
V
V=0: Horizontal addressing mode; V=1: Vertical addressing mode. H is used to select the extended instruction set. Please refer to the instruction table.
H
Read Status
A0
0
R/W(/WR)
1
D7
PD
D6
0
D5
D
D4
E
D3
XD
D2
MY
D1
V
D0
MLB
Flag
PD PD=0: Chip is active; PD=1: Chip is in power down mode.
Description
D
0 D, E 0 1 1
E
0 1 0 1 All Segments ON Normal mode
Display Mode
Display Blank (DDRAM Data is masked out)
Inverse Display mode
XD
0 XD, MY 0 1 1
MY
0 1 0 1
Display Mode
Only horizontal direction is mirrored. Both horizontal and vertical direction is mirrored. Normal direction. Only vertical direction is mirrored.
Select Vertical or Horizontal addressing mode. V MLB V=0: Horizontal addressing mode; V=1: Vertical addressing mode. Data Format. MLB=0: LSB on top; MLB=1: MSB on top.
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Read Data
Read the specified 8-bit data in DDRAM to the microprocessor. The location is specified by the X-address and Y-address.
A0
1
R/W(/WR)
1
D7
D6
D5
D4
D3
D2
D1
D0
Read Data
Write Data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written.
A0
1
R/W(/WR)
0
D7
D6
D5
D4
D3
D2
D1
D0
Read Data
NOP
No operation.
A0
0
R/W(/WR)
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Reset
This is the Software RESET instruction. This is same as hardware reset.
A0
0
R/W(/WR)
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
1
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[ H=0 ]
When Function Set instruction sets H=0, the selected instruction descriptions are as below.
End Read-Modify-Write
This command releases the Read-Modify-Write mode, and returns the column and row address to the address it was at when the mode was entered.
A0
0
R/W(/WR)
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
1
D1
1
D0
0
Enable Read-Modify-Write
This command is used paired with the "End Read-Modify-Write" instruction. Once this command has been input, the display data read command does not change the column and row address, but only the display data write command increments (+1) the address depend on V register setting. This mode is maintained until the END command is input. When the END command is input, the address returns to the address it was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor.
A0
0
R/W(/WR)
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
1
D1
1
D0
1
* Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.
Read-Modify-Write Page Address Set Column Address Set Read-Modify-Write Cycle Dummy Read Data Read Modify Data Data Write (at same Address)
No
Finished?
Yes
Done
Display Control
The bits D and E configure the display mode.
A0
0
R/W(/WR)
0
D7
0
D6
0
D5
0
D4
0
D3
1
D2
D
D1
0
D0
E
Flag D
0 D, E 0 1 1
Description E
0 1 0 1 All Segments ON Normal mode Inverse Display mode
Display Mode
Display Blank (Segments will always output non-selected waveform)
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Frame Rate
This command is used to select the frame rate.
A0
0 range)
R/W(/WR)
0
D7
0
D6
0
D5
0
D4
1
D3
0
D2
FR2
D1
FR1
D0
FR0
The optional Frame Rates are: (no matter 1/33, 1/17 or 1/9 duty mode, the frame rate will be controlled in the specified
FR2
0 0 0 0 1 1 1 1
FR1
0 0 1 1 0 0 1 1
FR0
0 1 0 1 0 1 0 1
Frame Rate
60 Hz 65 Hz 70 Hz 73 Hz (Default) 76 Hz 80 Hz 85 Hz 90 Hz
Set Y address of DDRAM
Y[2:0] specifies the Y address of the Display Data RAM (DDRAM).
A0
0
R/W(/WR)
0
D7
0
D6
1
D5
0
D4
0
D3
0
D2
Y2
D1
Y1
D0
Y0
Y2
0 0 0 0 1
Y1
0 0 1 1 0
Y0
0 1 0 1 0
Addressed Page
Page0 Page1 Page2 Page3 Page4
Allowed X address
0 ~ 131 0 ~ 131 0 ~ 131 0 ~ 131 0 ~ 131
Valid bit (MLB= "H")
D7~D0 D7~D0 D7~D0 D7~D0 D7
Set X address of DDRAM
Specify the X address to point the columns of the Display Data RAM (DDRAM). The valid range is 0~131.
Set X address of DDRAM (Low) A0
0
R/W(/WR)
0
D7
1
D6
0
D5
0
D4
0
D3
X3
D2
X2
D1
X1
D0
X0
Set X address of DDRAM (High) A0
0
R/W(/WR)
0
D7
1
D6
0
D5
0
D4
1
D3
X7
D2
X6
D1
X5
D0
X4
X7
0 0 0 : 1 1 1
X6
0 0 0 : 0 0 0
X5
0 0 0 : 0 0 0
X4
0 0 0 : 0 0 0
X3
0 0 0 : 0 0 0
X2
0 0 0 : 0 0 0
X1
0 0 1 : 0 1 1
X0
0 1 0 : 1 0 1
Column Address
0 1 2 : 129 130 131
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[ H=1 ]
When Function Set instruction sets H=1, the selected instruction descriptions are as below.
Display Duty
This instruction configures the display duty.
A0
0
R/W(/WR)
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
1
D1
PS
D0
WS
Flag
Use PS and WS to select the duty.
Description PS WS
X 0 1
Display Duty
1:33 (32 commons + 1 ICON common) 1:9 (8 commons + 1 ICON common) 1:17 (16 commons + 1 ICON common)
PS, WS
0 1 1
Booster Control
This instruction configures the built-in voltage booster.
A0
0
R/W(/WR)
0
D7
0
D6
0
D5
0
D4
0
D3
1
D2
BE
D1
PC1
D0
PC0
Flag
Description
ST7573 supports software configurable Booster Efficiency. Customers can change the BE and PC[1:0] according to the LCD panel loading and their power consumption requirement. The higher level provides higher driving ability while the power consumption is also higher.
BE
BE
0 1
Booster Efficiency Level
Booster Efficiency Level 2 (Default) Booster Efficiency Level 1
ST7573 supports software selectable Booster Stage. Customers can change the BE[1:0] and PC[1:0] according to the LCD panel loading and their power consumption requirement. The higher stage generates higher driving ability while the power consumption is also higher. PC[1:0]
PC1
0 1
PC0
1 X
Booster Stage
Booster X3 Booster X4
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Display Part
This instruction configures the partial display part.
A0
0
R/W(/WR)
0
D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
DP1
D0
DP0
Flag DP1
DP[1:0] 0 0 1 1
Description
Use DP[1:0] to select the start common for partial display.
DP0
0 1 0 1
Start common
COM0 COM8 COM16 N/A
Start page
Page 0 Page 1 Page 2
*The range of display common depends on the instruction of "Display Partial". For Example, if Duty=1/17 and DP[1:0]=01, then display common is COM8 to COM23 and CONS is at page 5. *The function of partial display is ineffective when Duty=1/33.
BIAS System
ST7573 is built-in a BIAS-voltage generation system for driving the LCD. The bias can be specified by this instruction.
A0
0
R/W(/WR)
0
D7
0
D6
0
D5
0
D4
1
D3
0
D2
1
D1
BS1
D0
BS0
The referential settings of Bias, Duty and V0 are listed below: LCD voltage
BS1
0 0 1 1
BS0
0 1 0 1
BIAS
7 6 5 4
Recommend Duty
1/33 1/33, 1/17 1/17, 1/9 1/9
Symbol
V0 VG VM VSS
Voltage for 1/5 BIAS
V0 2/5 of V0 1/5 of V0 VSS
* Be sure the VG is in operable range: (1.28V VG VDD2-0.2V) in any operation condition.
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Set V0
Set V0 voltage level into this register and the built-in voltage regulator will generate the V0.
A0
0
R/W(/WR)
0
D7
1
D6
VOP6
D5
VOP5
D4
VOP4
D3
VOP3
D2
VOP2
D1
VOP1
D0
VOP0
The V0 voltage can be calculated by this formula: V0=( a + VOP[6:0] x b ) ..................................................................(1)
Figure 19 V0 voltage vs. VOP[6:0] value
The parameters in this formula are controlled by the hardware pin "PM" (Ta=25 C).
H/W Setting
PM="L" PM="H"
a
3.0 4.5
b
0.03 0.03
Unit
V V
Set Start Line (Vertical-Scroll)
Sets the line address of display RAM to determine the initial display line instruction. The RAM display data is displayed at the top of row (COM0) of LCD panel.
A0
0
R/W(/WR)
0
D7
0
D6
1
D5
0
D4
S4
D3
S3
D2
S2
D1
S1
D0
S0
S4
0 0 0 : : : 1 1
S3
0 0 0 : : : 1 1
S2
0 0 0 : : : 1 1
S1
0 0 1 : : : 1 1
S0
0 1 0 : : : 0 1
Column address
0 1 2 : : : 30 31
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11. Instruction Sequence
This section introduces some reference instruction flows.
Power ON flow with built-in power circuits:
Figure 20 Initial flow with built-in Power Supply Circuits POWER SEQUENCE
1. tV2ON: Period between VDD and VDD2 turned ON. => 0 ms (min). No maximum value specified. 2. tRSTL: Reset Low time after VDD is stable. => 0 ms (min). No maximum value specified. 3. tRW: Reset low pulse width. Please refer to RESB timing specification (Page30).
Power Sequence
tRW tRSTL tV2ON
RESB VDD2 VDD
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Power Saving flow with built-in power circuits
ENTERING THE POWER SAVE MODE
The power save mode is achieved by setting PD bit to be "1". No specified instruction flow required.
EXITING THE POWER SAVE MODE
Figure 21 Exiting Power Save Mode INTERNAL SEQUENCE of EXIT POWER SAVE MODE
After receiving the "PD" is "L", the internal circuits (Power and COM/SEG) will starts the following procedure.
Data
PD="L"
/WR
Booster
Max: 100ms
tBON
Regulator
Max: 100ms
tRON
Follower COM, SEG
Note: 1. 2.
Max: 100ms
tFON tDON
Vss
Min: 160ms Max: 240ms
The power stable time is determined by LCD panel loading. The power stable time in this figure is base on: LCD Panel Size = 1.5" with C1=1uF, C2=1uF.
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Power OFF flow with built-in power circuits
USING PD BIT
By setting PD="H", ST7573 will go into power save mode. The LCD driving outputs are all fixed to VSS and the built-in power circuits are turned OFF. After the built-in power circuits are turned OFF, the power (VDD and VDD2) can be removed.
Instruction Flow
Note: 1. 2. 3. 4. 5. 6. 7. 8. tIPOFF: Internal Power discharge time. => 250ms (max). tV2OFF: Period between VDD and VDD2 OFF time. => 50 ms (max). It is NOT recommended to turn VDD OFF before VDD2. Without VDD, the internal status cannot be guaranteed and internal discharge-process maybe stopped. The un-discharged power maybe polarizes the liquid crystal in panel. IC will NOT be damaged if either VDD or VDD2 is OFF while another is ON. The timing is dependent on panel loading and the external capacitor(s). The timing in these figures is base on the condition that: LCD Panel Size = 1.5" with C1=1uF, C2=1uF. Reset Low time after VDD2 is stable. When turning VDD2 OFF, the falling time should follow the specification: 300ms tPFall 1sec
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12 Absolutely Maximum Rating
In accordance with the Absolute Maximum Rating values; see notes 1 and 2. Parameter Digital Power Supply Voltage Analog Power supply voltage LCD Driver Power supply voltage Input voltage Operating temperature Storage temperature Symbol VDD VDD2 V0-XV0 VG, VM VIN TOPR TSTR Conditions Unit V V V V V C C
-0.3 ~ 3.6 -0.3 ~ 3.6 -0.3 ~ 9.5 -0.3 ~ VDD2+0.3 -0.3 ~ VDD+0.3 -30 to +85 -65 to +150
Figure 22 Voltage Range
Notes
1. 2. 3. Stresses over the Absolutely Maximum Rating may cause permanent damage to the device. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise specified. Make sure the voltage of the following pins follows the relation list below: V0 VDD2 VG VM VSS XV0
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13. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices").
14. DC CHARACTERISTICS
Unless otherwise specified, VSS = 0V; Tamb = -30C to +85 C. Item Operation Voltage (1) Symbol VDD VDD2 Vop VGO VIHC VILC VOHC VOLC ILI ILO RON FR Ta = 25 C V0 = 6.0 V VG = 2.4 V IOUT=-1mA; VDD=2.4V IOUT=1mA; VDD=2.4V Condition Rating Min. 2.4 2.4 3.0 1.28 0.7 x VDD VSS 0.8 x VDD VSS -- -- -- -- -- -- 0.8 0.8 73 Typ. -- -- -- Max. 3.6 3.6 9.0 VDD2 VDD 0.3 x VDD VDD 0.2 x VDD 1.0 3.0 -- -- 77 V V V V Unit V V V V0, XV0 VGO Applicable Pin
Power
Operating Voltage (2) V0-XV0 Internal VG Output
High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current Liquid Crystal Driver ON Resistance Frame Rate
-1.0 -3.0
-- -- 69
A A
K Hz COMn SEGn
V=10%
FR[2:0]=011b, Ta = 25 C
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Dynamic Current Consumption: During Display, with Internal Power Supply ON, current consumed by whole chip (bare die) Test pattern Display Pattern SNOW Power Down Symbol Condition VDD = VDD2 = 2.8V, Frame Rate = 73 Hz; Booster X4; V0 = 6.9 V; Bias=1/7; 1/33 Duty VDD = VDD2 = 2.8V, Ta = 25 C Rating Min. -- -- Typ. 85 0.5 Max. -- 10 Units Notes
ISS ISS
A A
Notes to the DC characteristics
1. 2. The maximum V0 voltage may be generated will be limited by VDD2 , temperature and panel loading. Power Down: During power down mode, all static currents are switched off.
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15. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics (For the 8080 Series MPU)
Figure 23
VDD = 2.4~3.3V
Item
Address setup time Address hold time System cycle time /WR low pulse width /WR high pulse width /RD low pulse width /RD high pulse width WRITE Data setup time WRITE Data hold time READ access time READ output disable time
Signal
A0
Symbol
tAW8 tAH8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8
Condition
Rating Min.
15 10 150 80 70 243 70 30 35 30 243 70
Typ.
Max.
Units
/WR /RD
ns
D0 ~ D7
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between CSB being "L" and WR and RD being at the "L" level.
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System Bus Read/Write Characteristics (For the 6800 Series MPU)
VDD = 2.4~3.3V
Item
Address setup time Address hold time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ output disable time
Signal
A0
Symbol
tAW6 tAH6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6
Condition
Rating Min.
45 10 130 50 80 245 40 45 45 15 245 45
Typ.
Max.
Units
E/RD E/RD
ns
D0 ~ D7
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CSB being "L" and E.
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Serial Interface (4-Line Interface)
VDD = 2.4~3.3V
Item
Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time
Signal
Symbol
tSCYC
Condition
Rating Min.
330 165 165 10 60 10 40 10 110
Typ.
Max.
Units
SCL
tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
A0 SI CSB
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
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Serial Interface (3-Line Interface)
VDD = 2.4~3.3V
Item
Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time
Signal
Symbol
tSCYC
Condition
Rating Min.
330 165 165 20 30 10 120
Typ.
Max.
Units
SCL
tSHW tSLW tSDS tSDH tCSS tCSH
SI CSB
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
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Reset Timing
VDD = 2.4~3.3V
Item
Reset time Reset "L" pulse width
Signal
Symbol
tR
Condition
Rating Min.
2.0
Typ.
Max.
2.0
Units s s
RESB
tRW
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16. APPLICATION NOTE
Selection of Application Voltage
Power Range Summary Positive Booster: (VDD2 x PCn x BE) V0 or (VDD2 x PCn x BE) Vop; Negative Booster: [-VDD2 x (PCn - 1) x BE] XV0 or [VDD2 x (PCn -1) x BE] (Vop-VG), where VG = Vop x 2 / N; Vop requirement: [VDD2 x (PCn - 1) x BE] [Vop x (N-2) / N] or Vop VDD2 x (PCn -1) x BE x N / (N-2). PCn is the booster stage and BE is the booster efficiency. Referential values are listed below: (assume VDD2=2.8V) Module Size 1.5": BE=76% (min when Booster X4); Actual BE should be determined by module loading and ITO resistance value. 1.28 VG VDD2-0.2V. Recommend VG is: VDD2-VG around 0.5~0.8V. VM=VG/2 and 0.64V VM < VDD2. The worse condition should be considered: Low temperature effect and display on with snow pattern on panel (max: 1.8"). According to the Duty Size, the Recommend BIAS, Vop Range and Booster are listed below: VDD2=2.8V
Duty 33 17 9
Recommend BIAS
1/6 1/7 1/5 1/6 1/4
Recommend Vop Range
5.5 ~ 6.5 6.5 ~ 7.5 4.5 ~ 5.5 5.5 ~ 6.5 3.5 ~ 4.5
Recommend Booster
X4 X4 X3, X4 X4 X3, X4
The V0 range Tables are base on: LCD Panel Size = 1.5" with C1=1uF, C2=1uF. The actual V0 range depends on the Panel Size, Temperature Effect and Display Pattern.
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ITO Layout Reference (for Power)
V0O
V0S
VDD
FPC PIN
V0I
VDD2
Power Circuit Input, Output and Sensor ITO Layout (for V0, XV0 and VG ITO layout)
Digital / Analog Power ITO Layout (Using Single Power)
IC Side
V0O
ITO
RO
FPC
CAP
Note: 1. 2. 3. Total resistance value of VSS should be smaller than "VDD//VDD2". The relationship among input, output and sensor ITO (for V0, XV0 and VG) resistance value is RS > RO > RI . Recommend ITO resistance value: RI 150 Ohm; RO 200 Ohm; RS 250 Ohm.
RI
V0S
RS
V0I
XV0
Equivalent Circuit
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FPC PIN
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ST7573
MPU Interface
Intel 8080 series MPU Interface (8-bit):
32 COM0 ~ COM31 P1.7 to P1.0 8 D7 to D0 COMS 1
P3.0 P3.1 P3.2 P3.3 Intel 8051 Serial
A0 /RW /RD CSB ST7573
SEG0 ~ SEG131
132
Motorola 6800 series MPU Interface (8-bit):
32 COM0 ~ COM31 P1.0 to P1.7 8 DB0 to DB7 COMS 1
P3.0 P3.1 P3.2 P3.3 Intel 8051 Serial
A0 R/W E CSB ST7573
SEG0 ~ SEG131
132
Serial 4-Line SPI Mode:
32 COM0 ~ COM31 P1.6 P1.7 P3.0 P3.3 SDA SCL RS CSB SEG0 ~ SEG131 Intel 8051 Serial ST7573 132 COMS 1
Serial 3-Line SPI Mode:
32 1
COM0 ~ COM31 P1.6 P1.7 P3.0 P3.3 SDA SCL RS CSB SEG0 ~ SEG131 Intel 8051 Serial ST7573 COMS
132
Note: The Microprocessor Interface pins should not be left floating under any operation mode.
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C1 Reserve (Default NC)
Application Circuits
ST7573
6800 Interface
8080 Interface
System
VDD VDD2 VG VSS TP1 C2 D7 D6 D5 D4 D3 D2 D1 D0 E R/W A0 CSB RESB TP2
System
FPC
ITO
VDD2 VDD2 VDD VDD VDD DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse PS0 PS1 PS2 MLB T11 PM T10 VDD VDD VDD VDD2 VDD2 VDD2 VM VM VM VGI VGI VGI VGI VGS VGO VGO VSS VSS VSS V0O V0O V0S V0I V0I V0I V0I XV0I XV0I XV0I XV0I XV0S XV0O XV0O T1 T2 T3 T4 T0 T5 T6 T7 T8 T9 D7 D6 D5 D4 D3 D2 D1 D0 ERD RWR A0 CSB OSC RESB VRS VDD VDD VDD VDD VDD2 VDD2 VDD2 VDD2
Reserve Reserve Reserve COMS2 COM15 COM14
FPC
ITO
6800 Interface
8080 Interface
VDD2 VDD2 VDD VDD VDD DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse PS0 PS1 PS2 MLB T11 PM T10 VDD VDD VDD VDD2 VDD2 VDD2 VM VM VM VGI VGI VGI VGI VGS VGO VGO VSS VSS VSS V0O V0O V0S V0I V0I V0I V0I XV0I XV0I XV0I XV0I XV0S XV0O XV0O T1 T2 T3 T4 T0 T5 T6 T7 T8 T9 D7 D6 D5 D4 D3 D2 D1 D0 ERD RWR A0 CSB OSC RESB VRS VDD VDD VDD VDD VDD2 VDD2 VDD2 VDD2
Reserve Reserve Reserve COMS2 COM15 COM14
PS2="H PS1="H PS0="L C1=0.1~1uF C2=0.1~1uF OSC="H MLB="L PM="L T0~T8=Open T9="L T10="H T11="H Clock: Internal Data Format: LSB Upper V0 Range: Lower range
PS2="L PS1="H PS0="L C1=0.1~1uF C2=0.1~1uF OSC="H MLB="H PM="H T0~T8=Open T9="L T10="H T11="H Clock: Internal Data Format: MSB Upper V0 Range: Higher range
COM1 COM0 SEG131 SEG130 SEG129 SEG128 SEG127
COM1 COM0 SEG131 SEG130 SEG129 SEG128 SEG127
VDD VDD2 C1 TP1 Reserve (Default NC) C2 D7 SEG4 SEG3 SEG2 SEG1 SEG0 Reserve Reserve COMS1 COM16 COM17 COM18 D6 D5 D4 D3 D2 D1 D0 /RD /WR A0 CSB RESB TP2 VG VSS
SEG4 SEG3 SEG2 SEG1 SEG0 Reserve Reserve COMS1 COM16 COM17 COM18
2007/07/12
COM29 COM30 COM31
COM29 COM30 COM31
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ST7573
Notes for all applications:
C1 Reserve (Default NC)
Serial 3-Line SPI
Serial 4-Line SPI
System
System
FPC
ITO
VDD2 VDD2 VDD VDD VDD DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse PS0 PS1 PS2 MLB T11 PM T10 VDD VDD VDD VDD2 VDD2 VDD2 VM VM VM VGI VGI VGI VGI VGS VGO VGO VSS VSS VSS V0O V0O V0S V0I V0I V0I V0I XV0I XV0I XV0I XV0I XV0S XV0O XV0O T1 T2 T3 T4 T0 T5 T6 T7 T8 T9 D7 D6 D5 D4 D3 D2 D1 D0 ERD RWR A0 CSB OSC RESB VRS VDD VDD VDD VDD VDD2 VDD2 VDD2 VDD2
Reserve Reserve Reserve COMS2 COM15 COM14
FPC
ITO
Serial SPI-3
Serial SPI-4
VDD2 VDD2 VDD VDD VDD DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse Reverse PS0 PS1 PS2 MLB T11 PM T10 VDD VDD VDD VDD2 VDD2 VDD2 VM VM VM VGI VGI VGI VGI VGS VGO VGO VSS VSS VSS V0O V0O V0S V0I V0I V0I V0I XV0I XV0I XV0I XV0I XV0S XV0O XV0O T1 T2 T3 T4 T0 T5 T6 T7 T8 T9 D7 D6 D5 D4 D3 D2 D1 D0 ERD RWR A0 CSB OSC RESB VRS VDD VDD VDD VDD VDD2 VDD2 VDD2 VDD2
Reserve Reserve Reserve COMS2 COM15 COM14
PS2="H PS1="L PS0="L C1=0.1~1uF C2=0.1~1uF
PS2="L PS1="L PS0="L C1=0.1~1uF C2=0.1~1uF
The Microprocessor Interface pins should not be left floating under any operation mode.
Recommend short noisy nets by FPC (refer to Page 41, ITO Layout).
OSC="H MLB="L PM="H T0~T8=Open T9="L T10="H T11="H Clock: Internal Data Format: LSB Upper V0 Range: Higher range
OSC="H MLB="H PM="L T0~T8=Open T9="L T10="H T11="H Clock: Internal Data Format: MSB Upper V0 Range: Lower range
COM1 COM0 SEG131 SEG130 SEG129 SEG128 SEG127
COM1 COM0 SEG131 SEG130 SEG129 SEG128 SEG127
VDD VDD2 VG VSS
VDD VDD2 C1 VG VSS
TP1 C2 TP2 SDA SCLK CSB RESB
TP1 Reserve (Default NC)
SEG4 SEG3 SEG2 SEG1 SEG0 Reserve Reserve COMS1 COM16 COM17 COM18
SDA SCLK
SEG4 SEG3 SEG2 SEG1 SEG0 Reserve Reserve COMS1 COM16 COM17 COM18
C2 TP2 A0 CSB RESB
COM29 COM30 COM31
COM29 COM30 COM31
ST7573
Reversion History
Version
0.0 Initial version Modify Chip Thickness, PAD arrangement and PAD number (Page2) Modify Pin count and Pin description of Test Pin (Page9~Page10) 0.1 Modify the I/O pin resistance limitation of T[0:11] (Page10) Modify the Application circuit (Page49~Page51) Modify Fig24 and Fig25 (Page32) Modify Driver Output Circuits (Page 1) Modify Chip Size (Page 2) Modify description of PD (Page 25) 0.1a Modify description of Frame Rate (Page28) Modify instruction of Display Part (Page 30) Modify Fig24 and Fig25 (Page 32) Modify test condition (Page 36) 0.1b Modify pin description (Page 8) Modify application circuit. (Page 50~Page 51) Modify Voltage regulation temperature gradient (Page 1) Reserve X2 Booster function 1.0 Reserve I2C Interface Modify DC field Update reference timing. Modify Fig2 and Fig 3 Modify the recommend BIAS, Vop rang and booster according to different duty size. 1.0a Define the relationship among Power Circuit Output, Input and Sensor ITO resistance value. Modify timing specification. 1.0b Modify Fig 12 Modify application circuit. 2007/07/12 2007/05/02 2007/0312 2007/02/01 2006/12/27 2006/08/15
Description
Date
2006/08/04
Ver 1.0b
46/46
2007/07/12

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